Generally, the testing of integrated circuits presents a number of technical challenges that significantly add to the cost of development and production. Specifically, there are two major difficulties that arise in the testing of integrated circuits. The first is accessibility to the individual components integrated onto the chip. The second is to provide complete test coverage while minimizing the added test structures on the chip required for testing all of the integrated product components.
Test structures take up additional space (i.e. chip area) that reduces the usable area of a chip or add to the overall chip area required for the end product. Test structures also cause undesirable parasitic loading of the integrated circuit components leading to performance degradation and spurious power consumption. Furthermore, the interface used to access the test structures is typically different from the actual integrated product interface; thus, once an integrated product is in the field it becomes difficult to identify and resolve even minor problems. Lastly, in many cases the interface to the test structures also requires that the chip (die) have more I/O (input/output) pads than would be required for only the actual integrated product, which in turn leads to a significant increase in the cost of packaging the chip.
One approach to overcome these challenges is to undertake the integrated circuit design with testability in mind from the start. So-called “design for testability” is a design practice that incorporates the required logic and testing modes for a particular integrated circuit into the integrated circuit design. However, there are many integrated circuits into which it is difficult and problematic to incorporate the required test structures into the design. In these cases there are typically severe performance degradations induced in the final product that result from the combination of the integrated circuit and the test structures.
A phase locked loop (PLL) is an example of an integrated circuit that suffers from the aforementioned performance degradations (as do synthesisers, delay lock loops and other circuits derived from the basic PLL topology). It is well understood that adding additional circuit elements within the loop typically has a negative impact on the cost and performance of the PLL (and other circuits derived from it). Therefore, test structures that do not add to the function of the loop have been considered a problem and have thus been avoided. This has lead to severe limitations on ability to test the individual components that make up a fully integrated PLL (or PLL-like) circuit. In many instances only the overall performance of PLL (or PLL-like) circuits could be tested, leaving the actual performance characteristics of the components to be ignored or inferred from the over-all performance of the PLL.
There is a desire to provide a testing method and apparatus that can be successfully integrated into a PLL that enables the isolation (for the purposes of testing and observation) of specific nodes and components of the PLL that are not easily accessible during normal operation. It is desirable that the testing method and apparatus can be added to a PLL without negatively impacting the performance or cost of the PLL. Specifically, it is desirable that the PLL integrated with the testing apparatus does not suffer from performance degradations during nominal (mission mode) operation. Furthermore, it is desirable that the PLL and the testing apparatus share the same interface so that additional input/output (I/O) pads are not required.